Low power latch design in near sub-threshold region to improve reliability for soft error.
Sandeep SriramHaiqing NanKen ChoiPublished in: ISQED (2011)
Keyphrases
- low power
- power consumption
- single chip
- low power consumption
- high speed
- low cost
- logic circuits
- vlsi architecture
- power dissipation
- cmos technology
- power reduction
- digital signal processing
- gate array
- high power
- mixed signal
- wireless transmission
- ultra low power
- real time
- nm technology
- image sensor
- energy saving
- multi channel
- hardware and software
- embedded systems