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Scalable 0.35V to 1.2V SRAM bitcell design from 65nm CMOS to 28nm FDSOI.
Fady Abouzeid
Audrey Bienfait
Kaya Can Akyel
Sylvain Clerc
Lorenzo Ciampolini
Philippe Roche
Published in:
ESSCIRC (2013)
Keyphrases
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cmos technology
nm technology
power consumption
low power
circuit design
high speed
power reduction
neural network
silicon on insulator
real time
metal oxide semiconductor
low cost
design principles
single chip
power dissipation
software architecture
data acquisition
building blocks
information systems