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Implementation of high precision/low latency FP divider using Urdhva-Tiryakbhyam multiplier for SoC applications.
C. Ravi Shankar Hanuman
J. Kamala
A. R. Aruna
Published in:
Des. Autom. Embed. Syst. (2020)
Keyphrases
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high precision
low latency
high recall
hardware implementation
high throughput
high speed
real time
high bandwidth
massive scale
highly efficient
achieve high precision
cost effective
mobile nodes
continuous query processing