An optimized hardware architecture of 4×4, 8×8, 16×16 and 32×32 inverse transform for HEVC.
Manel KammounEmna MaamouriAhmed Ben AtitallahNouri MasmoudiPublished in: ATSIP (2016)
Keyphrases
- hardware architecture
- high efficiency video coding
- hardware implementation
- hardware architectures
- video coding
- field programmable gate array
- multiview video coding
- associative memory
- processing elements
- low complexity
- motion estimation
- block matching motion estimation
- general purpose
- open source
- fine grained
- computer vision
- coding method
- xilinx virtex
- pattern recognition