A Hybrid Pipelined Architecture for High Performance Top-K Sorting on FPGA.

Weijie Chen Weijun Li Feng Yu

Published in: IEEE Trans. Circuits Syst. II Express Briefs (2020)

Keyphrases

pipelined architecture
field programmable gate array
hardware implementation
query processing
low power consumption
fpga implementation
embedded systems
high speed
signal processing
parallel computing
artificial intelligence
real time
data analysis
data processing
fine grained
high efficiency