MDE-Based Verification of SysML State Machine Diagram by UPPAAL.
Xiaopu HuangQingqing SunJiangwei LiTian ZhangPublished in: ISCTCS (2012)
Keyphrases
- state machine
- model checking
- formal methods
- finite state machines
- model checker
- state transition
- state machines
- temporal logic
- formal verification
- safety analysis
- symbolic model checking
- fault tolerant
- formal specification
- verification method
- timed automata
- reactive systems
- description language
- safety critical
- modeling language
- knowledge based systems
- distributed systems
- artificial intelligence
- databases
- building blocks
- control system