FPGA-based systolic deconvolution architecture for upsampling.
Alex Noel Joseph RajLianhong CaiWei LiZhemin ZhuangTardi TjahjadiPublished in: PeerJ Comput. Sci. (2022)
Keyphrases
- hardware architecture
- hardware implementation
- hardware architectures
- hardware design
- software architecture
- neural network
- image sequences
- real time
- least squares
- denoising
- kernel regression
- video processing
- systolic array
- image deconvolution
- dct domain
- application specific
- network architecture
- depth map
- low cost
- management system