A Low-Power Accelerator for Deep Neural Networks with Enlarged Near-Zero Sparsity.
Yuxiang HuanYifan QinYantian YouLi-Rong ZhengZhuo ZouPublished in: CoRR (2017)
Keyphrases
- low power
- neural network
- low cost
- power consumption
- high speed
- high power
- single chip
- pattern recognition
- vlsi architecture
- wireless transmission
- low power consumption
- digital signal processing
- vlsi circuits
- logic circuits
- cmos technology
- image sensor
- power reduction
- gate array
- real time
- delay insensitive
- associative memory
- computer simulation
- nm technology