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A Low Power, Low Chip Area, Two-stage Current-mode DAC Implemented in CMOS 130 nm Technology.
Jakub Dalecki
Rafal Dlugosz
Tomasz Talaska
Gunter Fischer
Published in:
MIXDES (2019)
Keyphrases
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nm technology
low power
power consumption
low cost
low power consumption
high speed
power dissipation
single chip
high power
cmos technology
mixed signal
vlsi architecture
logic circuits
vlsi circuits
digital signal processing
image sensor
power reduction
wide dynamic range
ultra low power