A memory efficient serial LDPC decoder architecture.

Abhiram Prabhakar Krishna Narayanan

Published in: ICASSP (5) (2005)

Keyphrases

memory efficient
ldpc codes
turbo codes
fpga implementation
multiple sequence alignment
low density parity check
iterative deepening
channel coding
decoding algorithm
multithreading
distributed source coding
external memory
distributed video coding
error correction
low complexity
motion estimation
data structure