A low-power 16×16-b parallel multiplier utilizing pass-transistor logic.
C. F. LawS. S. RofailK. S. YeoPublished in: IEEE J. Solid State Circuits (1999)
Keyphrases
- low power
- logic circuits
- high speed
- low cost
- power consumption
- delay insensitive
- single chip
- high power
- digital signal processing
- vlsi architecture
- vlsi circuits
- wireless transmission
- image sensor
- mixed signal
- power dissipation
- low power consumption
- power reduction
- parallel processing
- cmos technology
- floating point
- real time
- massively parallel
- gate array