A Scalable and Reconfigurable Bit-Serial Compute-Near-Memory Hardware Accelerator for Solving 2-D/3-D Partial Differential Equations.
Junjie MuChengshuo YuTony Tae-Hyoung KimBongjin KimPublished in: IEEE J. Solid State Circuits (2024)
Keyphrases
- partial differential equations
- field programmable gate array
- low cost
- hardware implementation
- image processing
- image denoising
- anisotropic diffusion
- compute intensive
- level set
- numerical solution
- virtual memory
- image enhancement
- numerical algorithms
- multiscale
- random number generator
- boundary value problem
- fourth order
- problems in image processing
- embedded systems
- conservation laws
- processor core
- energy functional
- image processing algorithms
- computing systems
- curve evolution
- high order
- commodity hardware
- efficient implementation
- diffusion equation
- denoising
- numerical scheme
- computer systems
- finite difference method
- processing elements
- hardware architecture
- finite difference
- computer architecture
- noise removal
- parallel implementation
- mathematical morphology
- multiresolution
- image analysis
- similarity measure