A low power and high speed 10 transistor full adder using multi threshold technique.

Akshay Bhaskar Dheeraj Reddy Shabhari Saravanan K. Jagannadha Naidu

Published in: ICIIS (2016)

Keyphrases

low power
high speed
logic circuits
power dissipation
power consumption
low cost
single chip
high power
vlsi circuits
wireless transmission
digital signal processing
frame rate
real time
low power consumption
cmos technology
power reduction
mixed signal
vlsi architecture
gate array
image sensor