Timing closure of clock enable signals on a 32 nm Intel Itanium processor.

Branimir Malnar Goran Zelic

Published in: MIPRO (2018)

Keyphrases

high speed
computer architecture
multi core processors
digital signal
fpga device
signal processing
parallel processing
computer systems
radio frequency
memory hierarchy
single instruction multiple data
power consumption
independent component analysis
instruction set
multiprocessor systems