DPA Resistant AES on FPGA Using Partial DDL.

Jens-Peter Kaps Rajesh Velegalati

Published in: FCCM (2010)

Keyphrases

high speed
field programmable gate array
signal processing
countermeasures
differential power analysis
low cost
partial information
neural network
data acquisition
s box
parallel hardware
embedded systems
hardware implementation
real time image processing
power analysis
advanced encryption standard