A 1.93TOPS/W Deep Learning Processor with a Reconfigurable Processing Element Array Based on SRAM Access Optimization.
Liao-Chuan ChenZhaofang LiYi-Jhen LinKuan-Pei LeeKea-Tiong TangPublished in: APCCAS (2022)
Keyphrases
- deep learning
- random access memory
- systolic array
- parallel architecture
- central processor
- unsupervised learning
- unsupervised feature learning
- machine learning
- high speed
- random access
- general purpose processors
- memory access
- processing elements
- pattern recognition
- mental models
- hardware implementation
- deep architectures
- power consumption
- general purpose
- image sensor
- weakly supervised
- low power
- image segmentation
- feature selection