Event-based verification of synchronous, globally controlled, logic designs against signal flow graphs.
Filip Van AeltenJonathan AllenSrinivas DevadasPublished in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (1994)
Keyphrases
- flow graphs
- asynchronous circuits
- flow graph
- verification method
- model checking
- signal processing
- non stationary
- high frequency
- event detection
- decision table
- bounded model checking
- automated reasoning
- linear time temporal logic
- epistemic logic
- model checker
- logic programming
- modal logic
- classical logic
- random walk
- image processing
- information flow
- frequency domain
- rough sets
- pattern recognition
- decision making
- flip flops
- formal methods
- event driven
- formal verification
- databases