Scalable hardware implementation for Quasi-Dyadic Goppa encoder.
Pedro Maat C. MassolinoCíntia Borges MargiPaulo S. L. M. BarretoWilson Vicente RuggieroPublished in: LASCAS (2014)
Keyphrases
- hardware implementation
- signal processing
- efficient implementation
- software implementation
- image processing algorithms
- fpga implementation
- hardware design
- low complexity
- field programmable gate array
- hardware architecture
- dedicated hardware
- bit rate
- motion estimation
- rate distortion
- pipeline architecture
- memory management
- low cost
- general purpose
- enhancement layer
- computational complexity
- image processing
- shift register
- neural network