Accuracy-Aware Memory Allocation to Mitigate BRAM Errors for Voltage Underscaling on FPGA Overlay Accelerators.
Tanvir AhmedJohannes Maximilian KühnPublished in: FPGA (2020)
Keyphrases
- high accuracy
- field programmable gate array
- error analysis
- single chip
- hardware implementation
- real time
- image processing
- classification accuracy
- error rate
- power supply
- verilog hdl
- parallel architecture
- overlay network
- highly accurate
- parallel processing
- data acquisition
- computational efficiency
- power system
- prediction accuracy
- high speed
- computational complexity