An advanced H.264/AVC CAVLC decoding architecture for low power implementation.
Byung-Yup LeeKwang-Ki RyooPublished in: NCM (2010)
Keyphrases
- low power
- vlsi architecture
- cmos technology
- power consumption
- low cost
- high speed
- low complexity
- deblocking filter
- low power consumption
- signal processor
- video decoder
- single chip
- decoding process
- vlsi implementation
- bit rate
- ultra low power
- real time
- mixed signal
- nm technology
- logic circuits
- inter frame
- bitstream
- video streams
- video coding
- hardware implementation
- low density parity check
- variable length coding
- analog to digital converter