Wooseok Byun

Publication Activity (10 Years)

Years Active: 2015-2024
Publications (10 Years): 8

Top Topics

Array Processor

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

IEEE Trans. Biomed. Circuits Syst.

Publications

Minseok Seo, Xuan Truong Nguyen, Seok Joong Hwang, Yongkee Kwon, Guhyun Kim, Chanwook Park, Ilkon Kim, Jaehan Park, Jeongbin Kim, Woojae Shin, Jongsoon Won, Haerang Choi, Kyuyoung Kim, Daehan Kwon, Chunseok Jeong, Sangheon Lee, Yongseok Choi, Wooseok Byun, Seungcheol Baek, Hyuk-Jae Lee, John Kim
IANUS: Integrated Accelerator based on NPU-PIM Unified Memory System. ASPLOS (3) (2024)
Sunyoung Park, Wooseok Byun, Minkyu Je, Ji-Hoon Kim
Algorithm-Hardware Co-Design for Wearable BCIs: An Evolution from Linear Algebra to Transformers. ISCAS (2024)
Wooseok Byun, Minkyu Je, Ji-Hoon Kim
An Energy-Efficient Domain-Specific Reconfigurable Array Processor With Heterogeneous PEs for Wearable Brain-Computer Interface SoCs. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (12) (2022)
Wooseok Byun, Minkyu Je, Ji-Hoon Kim
Advances in Wearable Brain-Computer Interfaces From an Algorithm-Hardware Co-Design Perspective. IEEE Trans. Circuits Syst. II Express Briefs 69 (7) (2022)
Wooseok Byun, Minkyu Je, Ji-Hoon Kim
A 2144.2-bits/min/mW 5-Heterogeneous PE-based Domain-Specific Reconfigurable Array Processor for 8-Ch Wearable Brain-Computer Interface SoC. VLSI Circuits (2021)
Yongjae Park, Su-Hyun Han, Wooseok Byun, Ji-Hoon Kim, Hyung-Chul Lee, Seong-Jin Kim
A Real-Time Depth of Anesthesia Monitoring System Based on Deep Neural Network With Large EDO Tolerant EEG Analog Front-End. IEEE Trans. Biomed. Circuits Syst. 14 (4) (2020)
Dokyun Kim, Wooseok Byun, Yunseo Ku, Ji-Hoon Kim
High-Speed Visual Target Identification for Low-Cost Wearable Brain-Computer Interfaces. IEEE Access 7 (2019)
Wooseok Byun, Dokyun Kim, Sung Yeon Kim, Ji-Hoon Kim
A 110.3-bits/min 8-Ch SSVEP-based Brain-Computer Interface SoC with 87.9% Accuracy. A-SSCC (2019)
Hyeji Kim, Injun Choi, Wooseok Byun, Jong-Yeol Lee, Ji-Hoon Kim
Distributed CRC Architecture for High-Radix Parallel Turbo Decoding in LTE-Advanced Systems. IEEE Trans. Circuits Syst. II Express Briefs (9) (2015)