Vyas Venkataraman

Publication Activity (10 Years)

Years Active: 2008-2009
Publications (10 Years): 0

Publications

Di Wang, Vyas Venkataraman, Zhen Wang, Wei Qin, Hangsheng Wang, Mrinal Bose, Jayanta Bhadra
Accelerating multi-party scheduling for transaction-level modeling. ACM Great Lakes Symposium on VLSI (2009)
Vyas Venkataraman, Di Wang, Atabak Mahram, Wei Qin, Mrinal Bose, Jayanta Bhadra
Synthesis Oriented Scheduling of Multiparty Rendezvous in Transaction Level Models. ISVLSI (2009)
Vyas Venkataraman, Di Wang, Wei Qin, Mrinal Bose, Jayanta Bhadra
Simulation of a Heterogeneous System at Multiple Levels of Abstraction Using Rendezvous Based Modeling. MTV (2009)
Konrad J. Kulikowski, Vyas Venkataraman, Zhen Wang, Alexander Taubin
Power Balanced Gates Insensitive to Routing Capacitance Mismatch. DATE (2008)
Konrad J. Kulikowski, Vyas Venkataraman, Zhen Wang, Alexander Taubin, Mark G. Karpovsky
Asynchronous balanced gates tolerant to interconnect variability. ISCAS (2008)