Shashi Kiran Chilappagari

Publication Activity (10 Years)

Years Active: 2006-2012
Publications (10 Years): 0

Top Venues

IEEE Trans. Inf. Theory

University of Arizona, Tucson, USA (PHD)

Education History

University of Arizona, Tucson, USA

PHD

Publications

Dung Viet Nguyen, Shashi Kiran Chilappagari, Michael W. Marcellin, Bane V. Vasic
On the Construction of Structured LDPC Codes Free of Small Trapping Sets. IEEE Trans. Inf. Theory 58 (4) (2012)
Shashi Kiran Chilappagari, Michael Chertkov, Bane V. Vasic
An Efficient Instanton Search Algorithm for LP Decoding of LDPC Codes Over the BSC. IEEE Trans. Inf. Theory 57 (7) (2011)
Shashi Kiran Chilappagari, Dung Viet Nguyen, Bane V. Vasic, Michael W. Marcellin
Error correction capability of column-weight-three LDPC codes under the Gallager A algorithm-Part II. IEEE Trans. Inf. Theory 56 (6) (2010)
Shiva Kumar Planjery, David Declercq, Shashi Kiran Chilappagari, Bane V. Vasic
Multilevel decoders surpassing belief propagation on the binary symmetric channel. ISIT (2010)
Shashi Kiran Chilappagari, Michael Chertkov, Bane V. Vasic
Worst Configurations (Instantons) for Compressed Sensing over Reals: a Channel Coding Approach CoRR (2010)
Shashi Kiran Chilappagari, Dung Viet Nguyen, Bane V. Vasic, Michael W. Marcellin
On trapping sets and guaranteed error correction capability of LDPC codes and GLDPC codes. IEEE Trans. Inf. Theory 56 (4) (2010)
Shashi Kiran Chilappagari, Michael Chertkov, Bane V. Vasic
Worst configurations (instantons) for Compressed Sensing over reals: A channel coding approach. ISIT (2010)
Shiva Kumar Planjery, Shashi Kiran Chilappagari, Bane V. Vasic, David Declercq, Ludovic Danjean
Iterative decoding beyond belief propagation. ITA (2010)
Dung Viet Nguyen, Bane Vasic, Michael W. Marcellin, Shashi Kiran Chilappagari
Structured LDPC codes from permutation matrices free of small trapping sets. ITW (2010)
Shiva Kumar Planjery, David Declercq, Shashi Kiran Chilappagari, Bane V. Vasic
Multilevel Decoders Surpassing Belief Propagation on the Binary Symmetric Channel CoRR (2010)
Dung Viet Nguyen, Bane V. Vasic, Michael W. Marcellin, Shashi Kiran Chilappagari
Structured LDPC Codes from Permutation Matrices Free of Small Trapping Sets CoRR (2010)
Dung Viet Nguyen, Shashi Kiran Chilappagari, Michael W. Marcellin, Bane V. Vasic
LDPC Codes from Latin Squares Free of Small Trapping Sets CoRR (2010)
Shashi Kiran Chilappagari, Bane V. Vasic, Mikhail G. Stepanov, Michael Chertkov
Analysis of error floors of LDPC codes under LP decoding over the BSC. ISIT (2009)
Shashi Kiran Chilappagari, David Declercq, Lucile Sassatelli, Bane V. Vasic
Two-bit message passing decoders for LDPC codes over the binary symmetric channel. ISIT (2009)
Shashi Kiran Chilappagari, Michael Chertkov, Mikhail G. Stepanov, Bane V. Vasic
Instanton-based Techniques for Analysis and Reduction of Error Floors of LDPC Codes CoRR (2009)
Bane Vasic, Shashi Kiran Chilappagari, Dung Viet Nguyen, Shiva Kumar Planjery
Trapping set ontology. Allerton (2009)
Shashi Kiran Chilappagari, Michael Chertkov, Mikhail G. Stepanov, Bane V. Vasic
Instanton-based techniques for analysis and reduction of error floors of LDPC codes. IEEE J. Sel. Areas Commun. 27 (6) (2009)
Shashi Kiran Chilappagari, Bane V. Vasic
Error-correction capability of column-weight-three LDPC codes. IEEE Trans. Inf. Theory 55 (5) (2009)
Lucile Sassatelli, Shashi Kiran Chilappagari, Bane V. Vasic, David Declercq
Two-Bit Message Passing Decoders for LDPC Codes Over the Binary Symmetric Channel CoRR (2009)
Shashi Kiran Chilappagari, Anantha Raman Krishnan, Bane Vasic
LDPC codes which can correct three errors under iterative decoding. ITW (2008)
Shashi Kiran Chilappagari, Dung Viet Nguyen, Bane V. Vasic, Michael W. Marcellin
On the guaranteed error correction capability of LDPC codes CoRR (2008)
Milos Ivkovic, Shashi Kiran Chilappagari, Bane V. Vasic
Eliminating Trapping Sets in Low-Density Parity Check Codes by using Tanner Graph Covers CoRR (2008)
Shashi Kiran Chilappagari, Anantha Raman Krishnan, Bane V. Vasic, Michael W. Marcellin
Low-Density Parity-Check Codes Which Can Correct Three Errors Under Iterative Decoding CoRR (2008)
Milos Ivkovic, Shashi Kiran Chilappagari, Bane V. Vasic
Eliminating Trapping Sets in Low-Density Parity-Check Codes by Using Tanner Graph Covers. IEEE Trans. Inf. Theory 54 (8) (2008)
Shashi Kiran Chilappagari, Dung Viet Nguyen, Bane V. Vasic, Michael W. Marcellin
On Trapping Sets and Guaranteed Error Correction Capability of LDPC Codes and GLDPC Codes CoRR (2008)
Shashi Kiran Chilappagari, Michael Chertkov
Provably Efficient Instanton Search Algorithm for LP decoding of LDPC codes over the BSC CoRR (2008)
Shashi Kiran Chilappagari, Dung Viet Nguyen, Bane Vasic, Michael W. Marcellin
Girth of the Tanner graph and error correction capability of LDPC codes. Allerton (2008)
Shashi Kiran Chilappagari, Dung Viet Nguyen, Bane V. Vasic, Michael W. Marcellin
Error Correction Capability of Column-Weight-Three LDPC Codes: Part II CoRR (2008)
Shashi Kiran Chilappagari, Anantha Raman Krishnan, Bane V. Vasic
LDPC Codes Which Can Correct Three Errors Under Iterative Decoding CoRR (2008)
Shashi Kiran Chilappagari, Dung Viet Nguyen, Bane V. Vasic, Michael W. Marcellin
On the guaranteed error correction capability of LDPC codes. ISIT (2008)
Shashi Kiran Chilappagari, Bane V. Vasic
Error Correction Capability of Column-Weight-Three LDPC Codes CoRR (2007)
Milos Ivkovic, Shashi Kiran Chilappagari, Bane Vasic
Designing LDPC Codes without small trapping sets by using Tanner Graph Covers. ISIT (2007)
Shashi Kiran Chilappagari, Bane V. Vasic
Reliable Memories Built from Unreliable Components Based on Expander Graphs CoRR (2007)
Bane V. Vasic, Shashi Kiran Chilappagari
An Information Theoretical Framework for Analysis and Design of Nanoscale Fault-Tolerant Memories Based on Low-Density Parity-Check Codes. IEEE Trans. Circuits Syst. I Regul. Pap. (11) (2007)
Shashi Kiran Chilappagari, Sundararajan Sankaranarayanan, Bane V. Vasic
Error Floors of LDPC Codes on the Binary Symmetric Channel. ICC (2006)
Shashi Kiran Chilappagari, Milos Ivkovic, Bane Vasic
Analysis of One Step Majority Logic Decoders Constructed From Faulty Gates. ISIT (2006)
Milos Ivkovic, Shashi Kiran Chilappagari, Bane V. Vasic
Construction of Memory Circuits Using Unreliable Components Based on Low-Density Parity-Check Codes. GLOBECOM (2006)

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Publication Activity (10 Years)

Top Venues

Shashi Kiran Chilappagari