Raymond R. Hoare

Publication Activity (10 Years)

Years Active: 2001-2014
Publications (10 Years): 0

Top Topics

Synthetic Aperture Radar

Machine Learning

Top Venues

Publications

Raymond R. Hoare, Denis Smetana
Accelerating SAR processing on COTS FPGA hardware using C-to-gates design tools. HPEC (2014)
Raymond R. Hoare, Zhu Ding, Alex K. Jones
A two-stage hardware scheduler combining greedy and optimal scheduling. J. Parallel Distributed Comput. 68 (11) (2008)
Ying Yu, Raymond R. Hoare, Alex K. Jones
A CAM-based intrusion detection system for single-packet attack detection. IPDPS (2008)
Alex K. Jones, Swapna R. Dontharaju, Shen Chih Tung, Leonid Mats, Peter J. Hawrylak, Raymond R. Hoare, James T. Cain, Marlin H. Mickle
Radio frequency identification prototyping. ACM Trans. Design Autom. Electr. Syst. 13 (2) (2008)
Alex K. Jones, Raymond R. Hoare, Joseph St. Onge, Joshua M. Lucas, Shuyi Shao, Rami G. Melhem
Linking Compilation and Visualization for Massively Parallel Programs. IPDPS (2007)
Zhu Ding, Raymond R. Hoare, Alex K. Jones, Rami G. Melhem
Interconnect routing and scheduling - Level-wise scheduling algorithm for fat tree interconnection networks. SC (2006)
Alex K. Jones, Raymond R. Hoare, Swapna R. Dontharaju, Shen Chih Tung, Ralph Sprang, Joshua Fazekas, James T. Cain, Marlin H. Mickle
A Field Programmable RFID Tag and Associated Design Flow. FCCM (2006)
Raymond R. Hoare, Ivan S. Kourtev, Alex K. Jones
Technology Mapping for Field Programmable Gate Arrays using Content-Addressable Memory (CAM). FCCM (2006)
Raymond R. Hoare, Alex K. Jones, Dara Kusic, Joshua Fazekas, John Foster, Shen Chih Tung, Michael L. McCloud
Rapid VLIW Processor Customization for Signal Processing Applications Using Combinational Hardware Functions. EURASIP J. Adv. Signal Process. 2006 (2006)
Alex K. Jones, Raymond R. Hoare, Dara Kusic, Justin Stander, Gayatri Mehta, Joshua Fazekas
A VLIW Processor With Hardware Functions: Increasing Performance While Reducing Power. IEEE Trans. Circuits Syst. II Express Briefs (11) (2006)
Ying Yu, Raymond R. Hoare, Alex K. Jones, Ralph Sprang
A hybrid encoding scheme for efficient single-cycle range matching in content addressable memory. ISCAS (2006)
Raymond R. Hoare, Zhu Ding, Alex K. Jones
Interconnect routing and scheduling - A near-optimal real-time hardware scheduler for large cardinality crossbar switches. SC (2006)
Jeffrey William Schuster, Kshitij Gupta, Raymond R. Hoare
Speech silicon AM: an FPGA-based acoustic modeling pipeline for hidden Markov model based speech recognition. IPDPS (2006)
Gayatri Mehta, Justin Stander, Joshua M. Lucas, Raymond R. Hoare, Brady Hunsaker, Alex K. Jones
A Low-Energy Reconfigurable Fabric for the SuperCISC Architecture. J. Low Power Electron. 2 (2) (2006)
Alex K. Jones, Swapna R. Dontharaju, Shen Chih Tung, Peter J. Hawrylak, Leonid Mats, Raymond R. Hoare, James T. Cain, Marlin H. Mickle
Passive active radio frequency identification tags. Int. J. Radio Freq. Identif. Technol. Appl. 1 (1) (2006)
Gayatri Mehta, Raymond R. Hoare, Justin Stander, Alex K. Jones
A Low-Energy Reconfigurable Fabric for the SuperCISC Architecture. FCCM (2006)
Gayatri Mehta, Raymond R. Hoare, Justin Stander, Alex K. Jones
Design space exploration for low-power reconfigurable fabrics. IPDPS (2006)
Alex K. Jones, Raymond R. Hoare, Swapna R. Dontharaju, Shen Chih Tung, Ralph Sprang, Joshua Fazekas, James T. Cain, Marlin H. Mickle
An automated, reconfigurable, low-power RFID tag. DAC (2006)
Zhu Ding, Raymond R. Hoare, Alex K. Jones, Dan Li, Shou-Kuo Shao, Shen-Chien Tung, Jiang Zheng, Rami G. Melhem
Switch Design to Enable Predictive Multiplexed Switching in Multiprocessor Networks. IPDPS (2005)
Raymond R. Hoare, Zhu Ding, Shen Chih Tung, Rami G. Melhem, Alex K. Jones
A framework for the design, synthesis and cycle-accurate simulation of multiprocessor networks. J. Parallel Distributed Comput. 65 (10) (2005)
Kevin J. Barker, Alan F. Benner, Raymond R. Hoare, Adolfy Hoisie, Alex K. Jones, Darren J. Kerbyson, Dan Li, Rami G. Melhem, Ramakrishnan Rajamony, Eugen Schenfeld, Shuyi Shao, Craig B. Stunkel, Peter Walker
On the Feasibility of Optical Circuit Switching for High Performance Computing Systems. SC (2005)
Joshua M. Lucas, Raymond R. Hoare, Ivan S. Kourtev, Alex K. Jones
LURU: global-scope FPGA technology mapping with content-addressable memories. ICECS (2004)
Ivan S. Kourtev, Raymond R. Hoare, Steven P. Levitan, Tom Cain, Bruce R. Childers, Donald M. Chiarulli, David L. Landis
Short Courses in System-on-a-Chip (SoC) Design. MSE (2003)
Raymond R. Hoare, D. Swope, S. Bailey
A Width Expansion of MMX/SIMD Processing Architecture on an FPGA. IASTED PDCS (2002)
Troy A. Johnson, Raymond R. Hoare
Cyclical Cascade Chains: A Dynamic Barrier Synchronization Mechanism for Multiprocessor Systems. IPDPS (2001)