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P. Suresh
ORCID
Publication Activity (10 Years)
Years Active: 1995-2024
Publications (10 Years): 14
Top Topics
Intrusion Detection
Hybrid Algorithms
Quantile Regression
High Utility
Top Venues
Wirel. Pers. Commun.
Neural Comput. Appl.
Comput. Syst. Sci. Eng.
Int. J. Appl. Pattern Recognit.
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Publications
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K. Nanthini
,
A. Tamilarasi
,
D. Sivabalaselvamani
,
P. Suresh
Automated classification of Alzheimer's disease based on deep belief neural networks.
Neural Comput. Appl.
36 (13) (2024)
P. Raja
,
P. Suresh
Variety of ovarian cysts detection and classification using 2D Convolutional Neural Network.
Multim. Tools Appl.
83 (16) (2024)
Disha Deotale
,
Madhushi Verma
,
P. Suresh
,
Neeraj Kumar
Physiotherapy-based human activity recognition using deep learning.
Neural Comput. Appl.
35 (15) (2023)
S. R. Vijayakumar
,
P. Suresh
Sales Demand Forecasting in Car Industry Using Seagull Optimization Based Holt Winter and Quantile Regression Neural Network.
Wirel. Pers. Commun.
133 (1) (2023)
S. R. Vijayakumar
,
P. Suresh
Lean based cycle time reduction in manufacturing companies using black widow based deep belief neural network.
Comput. Ind. Eng.
173 (2022)
M. Anuradha
,
G. Mani
,
T. Shanthi
,
N. R. Nagarajan
,
P. Suresh
,
C. Bharatiraja
Intrusion Detection System for Big Data Analytics in IoT Environment.
Comput. Syst. Sci. Eng.
43 (1) (2022)
Madhumitha Kulandaivel
,
Arulanand Natarajan
,
Sathiyamoorthi Velayutham
,
Ashutosh Srivastava
,
Sachin Kumar Gupta
,
P. Suresh
,
Nitin Goyal
Compressive Sensing Node Localization Method Using Autonomous Underwater Vehicle Network.
Wirel. Pers. Commun.
126 (3) (2022)
R. Karthikeyan
,
A. Celine Kavida
,
P. Suresh
Deep Root Memory Optimized Indexing Methodology for Image Search Engines.
Comput. Syst. Sci. Eng.
40 (2) (2022)
Logeswaran K.
,
P. Suresh
High utility itemset mining using genetic algorithm assimilated with off policy reinforcement learning to adaptively calibrate crossover operation.
Comput. Intell.
38 (5) (2022)
P. Suresh
,
K. R. Radhika
Nature inspired hybrid algorithms for binding shared key with user trait.
Int. J. Appl. Pattern Recognit.
6 (3) (2021)
P. Suresh
,
R. Sukumar
,
S. Ayyasamy
Efficient pattern matching algorithm for security and Binary Search Tree (BST) based memory system in Wireless Intrusion Detection System (WIDS).
Comput. Commun.
151 (2020)
S. Padmavathy
,
P. Suresh
Fetal Ultrasound Image Evaluation of Chromosomal Anomaly Detection and Classification Using Conditional Rooted Neural Network (CRNN).
J. Medical Imaging Health Informatics
9 (6) (2019)
K. Murugan
,
P. Suresh
Efficient Anomaly Intrusion Detection Using Hybrid Probabilistic Techniques in Wireless Ad Hoc Network.
Int. J. Netw. Secur.
20 (4) (2018)
S. Senthilkumar
,
P. Suresh
Analysis of Virtual Robot Movements for Performance Improvements in Personal Communication.
Wirel. Pers. Commun.
90 (2) (2016)
P. Suresh
,
T. Thayaparan
,
T. Obulesu
,
K. Venkataramaniah
Extracting Micro-Doppler Radar Signatures From Rotating Targets Using Fourier-Bessel Transform and Time-Frequency Analysis.
IEEE Trans. Geosci. Remote. Sens.
52 (6) (2014)
Swapnil Ashok Jadhav
,
Durvasula V. L. N. Somayajulu
,
S. Nagesh Bhattu
,
R. B. V. Subramanyam
,
P. Suresh
Topic dependent cross-word Spelling Corrections for Web Sentiment Analysis.
ICACCI
(2013)
Swapnil Ashok Jadhav
,
Durvasula V. L. N. Somayajulu
,
S. Nagesh Bhattu
,
R. B. V. Subramanyam
,
P. Suresh
Context Dependent Bag of words generation.
ICACCI
(2013)
K. S. Ravichandran
,
K. R. Sekar
,
P. Suresh
A Novel Approach for Optimal Grouping of Reusable Software Components for Component Based Software Development Systems.
Int. J. Softw. Eng. Knowl. Eng.
23 (7) (2013)
P. Suresh
,
R. Kesavan
Analysis of Supply Chain Network Using RFID Technique with Hybrid Algorithm
CoRR
(2010)
Rajesh Agarwal
,
Pinakpani Nayak
,
Manickam Malarvizhi
,
P. Suresh
,
Nina Modi
Virtual Quality Assurance Facilitation Model.
ICGSE
(2007)
S. K. Gupta
,
P. Suresh
,
Vasudha Bhatnagar
Incremental information mining.
Data Mining and Knowledge Discovery: Theory, Tools, and Technology
(2002)
P. Suresh
,
Rajat Moona
PERL-a registerless architecture.
HiPC
(1998)
S. Krishnakumar
,
P. Suresh
,
S. Sadashiva Rao
,
M. P. Pareek
,
R. Gupta
A single chip, pipelined, cascadable, multichannel, signal processor.
VLSI Design
(1995)