Nobuo Tsuda

Publication Activity (10 Years)

Years Active: 1989-2002
Publications (10 Years): 0

Publications

Nobuo Tsuda
Configurable PC Clusters Using a Hierarchical Complete-Connection-Based Switching Network. PRDC (2002)
Nobuo Tsuda
ABL-Tree: A Constant Diameter Interconnection Network for Reconfigurable Processor Arrays Capable of Distributed Communication . DFT (2001)
Nobuo Tsuda
Fault-Tolerant Processor Arrays Using Additional Bypass Linking Allocated by Graph-Node Coloring. IEEE Trans. Computers 49 (5) (2000)
Nobuo Tsuda, Tatsuyuki Shimizu
Reconfigurable Mesh-Connected Processor Arrays Using Row-Column Bypassing and Direct Replacement. ISPAN (2000)
Nobuo Tsuda
Fault-Tolerant Ring- and Toroidal Mesh-Connected Processor Arrays Able to Enhance Emulation of Hypercubes. DFT (2000)
Nobuo Tsuda
Fault-Tolerant Hierarchical Interconnection Networks Constructed by Additional Bypass Linking with Graph-Node Coloring. DFT (1997)
Nobuo Tsuda
Fault-Tolerant Shuffle-Exchange and de Bruijn Networks Capable of Quick Broadcasting. DFT (1996)
Nobuo Tsuda, Tsutomu Ishikawa, Yukihiro Nakamura
Totally defect-tolerant arrays capable of quick broadcasting. DFT (1995)
Mina Maruyama, Nobuo Tsuda, Kiyoshi Nakabayashi
A Rule-Embedded Neural-Network and Its Effectiveness in Pattern Recognition with III-Posed Conditions. IEICE Trans. Inf. Syst. (2) (1995)
Nobuo Tsuda
Defect- and fault-tolerant static ram module designs based on parity checking and automatic testing. Systems and Computers in Japan 24 (2) (1993)
Nobuo Tsuda
Hierarchical redundancy for two-dimensional orthogonal arrays using defect-tolerant replacement circuits. Systems and Computers in Japan 24 (2) (1993)
Nobuo Tsuda
Hierarchical redundancy for array-structure wsis. Systems and Computers in Japan 24 (7) (1993)
Tetsuji Satoh, Hideaki Takeda, Nobuo Tsuda
A Compact Multiway Merge Sorter using Linear-Array Comparators. FODO (1989)