Naga Durga Prasad Avirneni

Publication Activity (10 Years)

Years Active: 2007-2016
Publications (10 Years): 3

Top Topics

Power Management

Top Venues

IEEE Trans. Computers

PeerJ Comput. Sci.

Publications

Naga Durga Prasad Avirneni, Prem Kumar Ramesh, Arun K. Somani
Managing contamination delay to improve Timing Speculation architectures. PeerJ Comput. Sci. 2 (2016)
Naga Durga Prasad Avirneni, Prem Kumar Ramesh, Arun K. Somani
Managing contamination delay to improve Timing Speculation architectures. PeerJ Prepr. 4 (2016)
Naga Durga Prasad Avirneni, Prem Kumar Ramesh, Arun K. Somani
Utilization Aware Power Management in Reliable and Aggressive Chip Multi Processors. IEEE Trans. Computers 65 (3) (2016)
Naga Durga Prasad Avirneni, Prem Ramesh, Arun K. Somani
Managing contamination delay to improve Timing Speculation architectures. PeerJ Prepr. 3 (2015)
Naga Durga Prasad Avirneni, Arun K. Somani
Countering Power Analysis Attacks UsingReliable and Aggressive Designs. IEEE Trans. Computers 63 (6) (2014)
Naga Durga Prasad Avirneni, Arun K. Somani
Low Overhead Soft Error Mitigation Techniques for High-Performance and Aggressive Designs. IEEE Trans. Computers 61 (4) (2012)
Naga Durga Prasad Avirneni, Viswanathan Subramanian, Arun K. Somani
Low overhead Soft Error Mitigation techniques for high-performance and aggressive systems. DSN (2009)
Viswanathan Subramanian, Mikel Bezdek, Naga Durga Prasad Avirneni, Arun K. Somani
Superscalar Processor Performance Enhancement through Reliable Dynamic Clock Frequency Tuning. DSN (2007)