Maria Athanasaki

Publication Activity (10 Years)

Years Active: 2002-2006
Publications (10 Years): 0

Publications

Georgios I. Goumas, Nikolaos Drosinos, Maria Athanasaki, Nectarios Koziris
Message-passing code generation for non-rectangular tiling transformations. Parallel Comput. 32 (10) (2006)
Maria Athanasaki, Aristidis Sotiropoulos, Georgios Tsoukalas, Nectarios Koziris, Panayotis Tsanakas
Hyperplane Grouping and Pipelined Schedules: How to Execute Tiled Loops Fast on Clusters of SMPs. J. Supercomput. 33 (3) (2005)
Georgios I. Goumas, Nikolaos Drosinos, Maria Athanasaki, Nectarios Koziris
Automatic parallel code generation for tiled nested loops. SAC (2004)
Maria Athanasaki, Evangelos Koukis, Nectarios Koziris
Scheduling of Tiled Nested Loops onto a Cluster with a Fixed Number of SMP Nodes. PDP (2004)
Nikolaos Drosinos, Georgios I. Goumas, Maria Athanasaki, Nectarios Koziris
Delivering High Performance to Parallel Applications Using Advanced Scheduling. PARCO (2003)
Georgios I. Goumas, Maria Athanasaki, Nectarios Koziris
An Efficient Code Generation Technique for Tiled Iteration Spaces. IEEE Trans. Parallel Distributed Syst. 14 (10) (2003)
Georgios I. Goumas, Nikolaos Drosinos, Maria Athanasaki, Nectarios Koziris
Compiling Tiled Iteration Spaces for Clusters. CLUSTER (2002)
Georgios I. Goumas, Maria Athanasaki, Nectarios Koziris
Code Generation Methods for Tiling Transformations . J. Inf. Sci. Eng. 18 (5) (2002)
Georgios I. Goumas, Maria Athanasaki, Nectarios Koziris
Automatic code generation for executing tiled nested loops onto parallel architectures. SAC (2002)
Maria Athanasaki, Aristidis Sotiropoulos, Georgios Tsoukalas, Nectarios Koziris
A Pipelined Execution of Tiled Nested Loops on SMPs with Computation and Communication Overlapping. ICPP Workshops (2002)
Georgios I. Goumas, Nikolaos Drosinos, Maria Athanasaki, Nectarios Koziris
Data Parallel Code Generation for Arbitrarily Tiled Loop Nests. PDPTA (2002)
Maria Athanasaki, Aristidis Sotiropoulos, Georgios Tsoukalas, Nectarios Koziris
Pipelined scheduling of tiled nested loops onto clusters of SMPs using memory mapped network interfaces. SC (2002)