Leonardo J. Arnone

Publication Activity (10 Years)

Years Active: 2004-2023
Publications (10 Years): 3

Top Topics

Decoding Algorithm

Low Density Parity Check

Fpga Implementation

Top Venues

IEEE Embed. Syst. Lett.

Microprocess. Microsystems

Publications

Lucas A. Rabioglio, María C. Cebedio, Jorge Castiñeira Moreira, Leonardo J. Arnone
Middleton's Class A Noise Parameter Estimator. IEEE Embed. Syst. Lett. 15 (2) (2023)
Federico G. Krasser, Mónica C. Liberatori, Leonardo Coppolillo, Leonardo J. Arnone, Jorge Castiñeira Moreira
Fast and efficient FPGA implementation of Polar Codes and SoC test bench. Microprocess. Microsystems 84 (2021)
Mónica C. Liberatori, Leonardo J. Arnone, Jorge Castiñeira Moreira, Patrick Guy Farrell
Soft Distance Metric Decoding of Polar Codes. IMACC (2015)
Leonardo J. Arnone, Jorge Castiñeira Moreira, Patrick Guy Farrell
Field programmable gate arrays implementations of low complexity soft-input soft-output low-density parity-check decoders. IET Commun. 6 (12) (2012)
Patrick Guy Farrell, Leonardo J. Arnone, Jorge Castiñeira Moreira
Euclidean distance soft-input soft-output decoding algorithm for low-density parity-check codes. IET Commun. 5 (16) (2011)
C. M. Gonzalez, Hilda A. Larrondo, C. A. Gayoso, Leonardo J. Arnone, Eduardo I. Boemo
Digital Signal Transmission with Chaotic Encryption: Design and Evaluation of a FPGA Realization CoRR (2004)