Lambert Schaelicke

Publication Activity (10 Years)

Years Active: 1997-2009
Publications (10 Years): 0

Publications

Matthew A. Watkins, Sally A. McKee, Lambert Schaelicke
Revisiting Cache Block Superloading. HiPEAC (2009)
Matthew A. Watkins, Sally A. McKee, Lambert Schaelicke
A Phase-Adaptive Approach to Increasing Cache Performance. PACT (2007)
Lambert Schaelicke, Alan L. Davis
Design Trade-Offs for User-Level I/O Architectures. IEEE Trans. Computers 55 (8) (2006)
Lambert Schaelicke, Michael A. Parker
The design and utility of the ML-RSIM system simulator. J. Syst. Archit. 52 (5) (2006)
Lambert Schaelicke, Kyle B. Wheeler, Curt Freeland
SPANIDS: a scalable network intrusion detection loadbalancer. Conf. Computing Frontiers (2005)
Lambert Schaelicke
Evaluating the impact of the simulation environment on experimentation results. Perform. Evaluation 61 (4) (2005)
Timothy J. Dysart, Branden J. Moore, Lambert Schaelicke, Peter M. Kogge
Cache implications of aggressively pipelined high performance microprocessors. ISPASS (2004)
Branden J. Moore, Thomas Slabach, Lambert Schaelicke
Profiling Interrupt Handler Performance through Kernel Instrumentation. ICCD (2003)
Lambert Schaelicke, Thomas Slabach, Branden J. Moore, Curt Freeland
Characterizing the Performance of Network Intrusion Detection Sensors. RAID (2003)
Lixin Zhang, Zhen Fang, Michael A. Parker, Binu K. Mathew, Lambert Schaelicke, John B. Carter, Wilson C. Hsieh, Sally A. McKee
The Impulse Memory Controller. IEEE Trans. Computers 50 (11) (2001)
Lambert Schaelicke, Al Davis, Sally A. McKee
Profiling I/O Interrupts in Modern Architectures. MASCOTS (2000)
John B. Carter, Wilson C. Hsieh, Leigh Stoller, Mark R. Swanson, Lixin Zhang, Erik Brunvand, Al Davis, Chen-Chi Kuo, Ravindra Kuramkote, Michael A. Parker, Lambert Schaelicke, Terry Tateyama
Impulse: Building a Smarter Memory Controller. HPCA (1999)
John B. Carter, Wilson C. Hsieh, Mark R. Swanson, Lixin Zhang, Erik Brunvand, Al Davis, Chen-Chi Kuo, Ravindra Kuramkote, Michael A. Parker, Lambert Schaelicke, Leigh Stoller, Terry Tateyama
Memory System Support for Irregular Applications. LCR (1998)
Lambert Schaelicke, Al Davis
Improving I/O Performance with a Conditional Store Buffer. MICRO (1998)
Ulrich Brüning, Lambert Schaelicke
ATOLL: A High-Performance Communication Device for Massively Parallel Systems. APDC (1997)