Jian Wang

Publication Activity (10 Years)

Years Active: 1987-2021
Publications (10 Years): 3

Top Topics

Program Comprehension

Bug Localization

Top Venues

Publications

Weihua Liu, Erh-Wen Hu, Bogong Su, Jian Wang
Using machine learning techniques for DSP software performance prediction at source code level. Connect. Sci. 33 (1) (2021)
Erh-Wen Hu, Weihua Liu, Bogong Su, Jian Wang
Comparing DSP Software Performance Prediction Models at Source Code Level - From Analytical to Statistical. J. Softw. 14 (6) (2019)
Erh-Wen Hu, Bogong Su, Jian Wang
Software performance prediction at source level. SERA (2017)
Erh-Wen Hu, Cyril Ku, Andrew Russo, Bogong Su, Jian Wang
New DSP Benchmark based on Selectable Mode Vocoder (SMV). CDES (2006)
Bogong Su, Jian Wang, Erh-Wen Hu, Joseph B. Manzano
Software De-Pipelining Technique. SCAM (2004)
Bogong Su, Jian Wang, Rafi Rabipour, Erh-Wen Hu, Joseph B. Manzano
Loop optimization with tradeoff between cycle count and code size for DSP applications. EUSIPCO (2004)
Bogong Su, Jian Wang, Erh-Wen Hu, Joseph B. Manzano
De-pipeline a software-pipelined loop. ICASSP (2) (2003)
Jian Wang, Bogong Su, Erh-Wen Hu
A scalable loop optimization approach for scalable DSP processors. ICASSP (2000)
Bogong Su, Jian Wang, Andrew Esguerra
Source-level loop optimization for DSP code generation. ICASSP (1999)
Jian Wang, Bogong Su
Software pipelining of nested loops for real-time DSP applications. ICASSP (1998)
Jian Wang, Andreas Krall, M. Anton Ertl
Decomposed software pipelining with reduced register requirement. PACT (1995)
Jian Wang, Andreas Krall, M. Anton Ertl
Trace software pipelining. J. Comput. Sci. Technol. 10 (6) (1995)
Jian Wang, Andreas Krall, M. Anton Ertl, Christine Eisenbeis
Software pipelining with register allocation and spilling. MICRO (1994)
Jian Wang, Andreas Krall, M. Anton Ertl, Christine Eisenbeis
Trace Software Pipelining: A Novel Technique for Parallelization of Loops with Branches. IFIP PACT (1994)
Bogong Su, Stanley Habib, Wei Zhao, Jian Wang, Youfeng Wu
A study of pointer aliasing for software pipelining using run-time disambiguation. MICRO (1994)
Jian Wang, Christine Eisenbeis, Martin Jourdan, Bogong Su
Decomposed software pipelining: A new perspective and a new approach. Int. J. Parallel Program. 22 (3) (1994)
Jian Wang, Christine Eisenbeis, Bogong Su
Using timed Petri net to model instruction-level loop scheduling with resource constraints. J. Comput. Sci. Technol. 9 (2) (1994)
Jian Wang, Christine Eisenbeis
Decomposed Software Pipelining: A New Approach to Exploit Instruction Level Parallelism for Loop Programs. Architectures and Compilation Techniques for Fine and Medium Grain Parallelism (1993)
Bogong Su, Jian Wang, Zhizhong Tang, Chihong Zhang, Wei Zhao
URPR-1: A single-chip VLIW architecture. Microprocess. Microprogramming 39 (1) (1993)
Vicki H. Allan, Bogong Su, Pantung Wijaya, Jian Wang
Foresighted Instruction Scheduling Under Timing Constraints. IEEE Trans. Computers 41 (9) (1992)
Bogong Su, Jian Wang
: A New Global Software Pipelining Algorithm. MICRO (1991)
Bogong Su, Jian Wang, Zhizhong Tang, Wei Zhao, Yimin Wu
A software pipelining based VLIW architecture and optimizing compiler. MICRO (1990)
Bogong Su, Chunyi Shi, Kehong Wang, Peng Hu, Hao Shi, Jian Wang
The Architecture of a Distributed Knowledge Base System. DS-3 (1988)
Bogong Su, Jian Wang, Jinshi Xia
Global microcode compaction under timing constraints. MICRO (1988)
Bogong Su, Shiyuan Ding, Jian Wang, Jinshi Xia
GURPR - a method for global software pipelining. MICRO (1987)
Bogong Su, Shiyuan Ding, Jian Wang, Jinshi Xia
Microcode compaction with timing constraints. MICRO (1987)