Jean Oudinot

Publication Activity (10 Years)

Years Active: 2002-2008
Publications (10 Years): 0

Publications

Fahd Ben Abdeljelil, Benjamin Nicolle, William Tatinian, Lorenzo Carpineto, Jean Oudinot, Gilles Jacquemod
Application of Bottom-Up Methodology to RTW VCO. ISVLSI (2008)
Jean Oudinot
Top Verification of Low Power System with "Checkerboard" Approach. PATMOS (2006)
Benjamin Nicolle, William Tatinian, Jean Oudinot, Gilles Jacquemod
Scalable Model for Multi-Standard Phase Locked Loop. ICECS (2006)
Benjamin Nicolle, William Tatinian, Jean Oudinot, Gilles Jacquemod
Hierarchical Modeling of a Fractional Phase Locked Loop. PATMOS (2006)
Patricia Desgreys, Yannick Hervé, Jean Oudinot, S. Snaidero, Mohamed Karray
SoC modelling for virtual prototyping with VHDL-AMS. FDL (2004)
B. Hecker, M. Chavassieux, M. Laflutte, E. Beguin, L. Lagasse, Jean Oudinot
VHDL-AMS Library Development for Pacemaker Applications. DATE (2004)
Jean Oudinot, G. Overton, Aitor Endemaño Isasi, Marc P. Y. Desmulliez, Jean-Yves Fourniols, Sylvaine Muratet
Micromotor Simulation with VHDL-AMS. FDL (2003)
Jean Oudinot
The Most Complete Mixed-Signal Simulation Solution with ADVance MS. PATMOS (2003)
Jean Oudinot, Serge Scotti, Jean Ravatin, Audrey Le-clercq, Jacky Lebrun
Full Transceiver Circuit Simulation using VHDL-AMS. ESM (2002)