Hikaru Nakanishi

Publication Activity (10 Years)

Years Active: 1986-1995
Publications (10 Years): 0

Publications

Takashi Watanabe, Tsuyoshi Ohta, Tadanori Mizuno, Hikaru Nakanishi
Adaptive load balancing with bidirectional piggybacking. Systems and Computers in Japan 26 (10) (1995)
Shin-ya Kobayashi, Hikaru Nakanishi, Yoshikazu Tezuka, Takashi Watanabe
Modeling and analyzing advance processing control by extended message-passing. Systems and Computers in Japan 23 (6) (1992)
Shin-ya Kobayashi, Hikaru Nakanishi, Yoshikazu Tezuka, Makoto Furukawa
Permanent time-stamp ordering mechanism. Systems and Computers in Japan 23 (9) (1992)
Chanintorn Jittawiriyanukoon, Takashi Watanabe, Hikaru Nakanishi, Yoshikazu Tezuka
Approximate Analytic Method for Computer Systems with Multiple Level Concurrent Programs. INFOCOM (1989)
Chanintorn Jittawiriyanukoon, Hikaru Nakanishi, Yoshikazu Tezuka, Takashi Watanabe
Approximate performance evaluation of parallel processing systems using average concurrency. Systems and Computers in Japan 20 (11) (1989)
Takashi Watanabe, Hikaru Nakanishi, Hidehiko Sanada, Yoshikazu Tezuka
Simulation language based on logic for queueing network using time object. Systems and Computers in Japan 19 (6) (1988)
Kei Sato, Hikaru Nakanishi, Hidehiko Sanada, Yoshikazu Tezuka
D-SSQ: A queueing network simulator with parallel execution control. Systems and Computers in Japan 18 (3) (1987)
Takashi Watanabe, Hikaru Nakanishi, Hidehiko Sanada, Yoshikazu Tezuka
Performance evaluation of asynchronous distributed processing system with limited-advance processing. Systems and Computers in Japan 18 (9) (1987)
Hiroshi Suzuki, Hikaru Nakanishi, Hidehiko Sanada, Yoshikazu Tezuka, Ichiro Akiyoshi
Delay Analysis of Wait System Model for Window-Controlled Packet Network and Optimal Window Allocation. Systems and Computers in Japan 17 (3) (1986)
Miki Yamamoto, Hikaru Nakanishi, Hidehiko Sanada, Yoshikazu Tezuka, Ichiro Akiyoshi
Delay Analysis of Window Controlled Network with Finite Input Buffer. ICC (1986)