Farrukh Hijaz

Publication Activity (10 Years)

Years Active: 2011-2022
Publications (10 Years): 5

Top Topics

Embedded Processors

Interprocess Communication

Top Venues

ACM Trans. Archit. Code Optim.

IACR Cryptol. ePrint Arch.

Publications

Sofiane Chetoui, Rahul Shahi, Seif Abdelaziz, Abhinav Golas, Farrukh Hijaz, Sherief Reda
ARBench: Augmented Reality Benchmark For Mobile Devices. ISPASS (2022)
Sofiane Chetoui, Michael Chen, Abhinav Golas, Farrukh Hijaz, Adel Belouchrani, Sherief Reda
Alternating Blind Identification of Power Sources for Mobile SoCs. ICPE (2022)
Halit Dogan, Farrukh Hijaz, Masab Ahmad, Brian Kahne, Peter Wilson, Omer Khan
Accelerating Graph and Machine Learning Workloads Using a Shared Memory Multicore Architecture with Auxiliary Support for In-hardware Explicit Messaging. IPDPS (2017)
Qingchuan Shi, George Kurian, Farrukh Hijaz, Srinivas Devadas, Omer Khan
LDAC: Locality-Aware Data Access Control for Large-Scale Multicore Cache Hierarchies. ACM Trans. Archit. Code Optim. 13 (4) (2016)
Farrukh Hijaz, Qingchuan Shi, George Kurian, Srinivas Devadas, Omer Khan
Locality-aware data replication in the last-level cache for large scale multicores. J. Supercomput. 72 (2) (2016)
Masab Ahmad, Farrukh Hijaz, Qingchuan Shi, Omer Khan
CRONO: A Benchmark Suite for Multithreaded Graph Algorithms Executing on Futuristic Multicores. IISWC (2015)
Syed Kamran Haider, Masab Ahmad, Farrukh Hijaz, Astha Patni, Ethan Johnson, Matthew Seita, Omer Khan, Marten van Dijk
M-MAP: Multi-Factor Memory Authentication for Secure Embedded Processors. IACR Cryptol. ePrint Arch. 2015 (2015)
Syed Kamran Haider, Masab Ahmad, Farrukh Hijaz, Astha Patni, Ethan Johnson, Matthew Seita, Omer Khan, Marten van Dijk
M-MAP: Multi-factor memory authentication for secure embedded processors. ICCD (2015)
Masab Ahmad, Syed Kamran Haider, Farrukh Hijaz, Marten van Dijk, Omer Khan
Exploring the performance implications of memory safety primitives in many-core processors executing multi-threaded workloads. HASP@ISCA (2015)
Farrukh Hijaz, Brian Kahne, Peter Wilson, Omer Khan
Efficient parallel packet processing using a shared memory many-core processor with hardware support to accelerate communication. NAS (2015)
Farrukh Hijaz, Omer Khan
NUCA-L1: A Non-Uniform Access Latency Level-1 Cache Architecture for Multicores Operating at Near-Threshold Voltages. ACM Trans. Archit. Code Optim. 11 (3) (2014)
Qingchuan Shi, Farrukh Hijaz, Omer Khan
Towards efficient dynamic data placement in NoC-based multicores. ICCD (2013)
Farrukh Hijaz, Qingchuan Shi, Omer Khan
A private level-1 cache architecture to exploit the latency and capacity tradeoffs in multicores operating at near-threshold voltages. ICCD (2013)
Farrukh Hijaz, Qingchuan Shi, Omer Khan
Low-Latency Mechanisms for Near-Threshold Operation of Private Caches in Shared Memory Multicores. MICRO Workshops (2012)
Omer Khan, Henry Hoffmann, Mieszko Lis, Farrukh Hijaz, Anant Agarwal, Srinivas Devadas
ARCc: A case for an architecturally redundant cache-coherence architecture for large multicores. ICCD (2011)