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Debdut Biswas
ORCID
Publication Activity (10 Years)
Years Active: 2019-2024
Publications (10 Years): 4
Top Topics
Hurst Exponent
Power Dissipation
Enterprise Architecture
Multistage
Top Venues
IET Circuits Devices Syst.
VLSI Design
Circuits Syst. Signal Process.
Integr.
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Publications
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Debdut Biswas
A reference sampling ΔΣ subsampling PLL.
Integr.
96 (2024)
Debdut Biswas
Spur Reduction Circuit for Fractional-N PLLs.
Circuits Syst. Signal Process.
41 (5) (2022)
Debdut Biswas
,
Tarun Kanti Bhattacharyya
A Model of Spurs for Delta-Sigma Fractional PLLs.
VLSI Design
(2019)
Debdut Biswas
,
Tarun Kanti Bhattacharyya
Spur reduction architecture for multiphase fractional PLLs.
IET Circuits Devices Syst.
13 (8) (2019)