Dariusz Koscielnik

Publication Activity (10 Years)

Years Active: 2006-2023
Publications (10 Years): 12

Top Topics

Projections Onto Convex Sets

Compressive Sensing

Visual Interface

Signal Recovery

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Konrad Jurasz, Dariusz Koscielnik, Jakub Szyduczynski, Witold Machowski
A New Successive Time Balancing Time-to-Digital Conversion Method. Sensors 23 (24) (2023)
Konrad Jurasz, Dariusz Koscielnik, Jakub Szyduczynski, Marek Miskowicz
Systematization and Comparison of the Binary Successive Approximation Variants. Sensors 21 (24) (2021)
Jakub Szyduczynski, Dariusz Koscielnik, Konrad Jurasz, Marek Miskowicz
Successive Approximation Time-to-Digital Converters. EBCCSP (2020)
Jakub Szyduczynski, Viet Nguyen, Filippo Schembari, Robert Bogdan Staszewski, Dariusz Koscielnik, Marek Miskowicz
Behavioral Modelling and Optimization of a Cyclic Feedback-Based Successive Approximation TDC with Dynamic Delay Equalization. EBCCSP (2019)
Jakub Szyduczynski, Dariusz Koscielnik, Marek Miskowicz
A Successive Approximation Time-to-Digital Converter with Single Set of Delay Lines for Time Interval Measurements. Sensors 19 (5) (2019)
Dominik Rzepka, Marek Miskowicz, Dariusz Koscielnik, Nguyen T. Thao
Reconstruction of Signals From Level-Crossing Samples Using Implicit Information. IEEE Access 6 (2018)
Jakub Szyduczynski, Dariusz Koscielnik, Marek Miskowicz
Dynamic equalization of logic delays in feedback-based successive approximation TDCs. EBCCSP (2017)
Dominik Rzepka, Miroslaw Pawlak, Dariusz Koscielnik, Marek Miskowicz
Bandwidth Estimation From Multiple Level-Crossings of Stochastic Signals. IEEE Trans. Signal Process. 65 (10) (2017)
Dominik Rzepka, Dariusz Koscielnik, Marek Miskowicz
Clockless signal-dependent compressive sensing of multitone signals using time encoding machine. EBCCSP (2017)
Dominik Rzepka, Dariusz Koscielnik, Marek Miskowicz, Nguyen T. Thao
Signal recovery from level-crossing samples using projections onto convex sets. EBCCSP (2016)
Dariusz Koscielnik, Dominik Rzepka, Jakub Szyduczynski
Sample-and-Hold Asynchronous Sigma-Delta Time Encoding Machine. IEEE Trans. Circuits Syst. II Express Briefs (4) (2016)
Dariusz Koscielnik, Jakub Szyduczynski, Dominik Rzepka, Wojciech Andrysiewicz, Marek Miskowicz
Optimized design of successive approximation time-to-digital converter with single set of delay lines. EBCCSP (2016)
Marek Miskowicz, Jakub Szyduczynski, Dariusz Koscielnik
Analytical approach to multiple memoryless backoff contention analysis. WFCS (2015)
Wojciech Andrysiewicz, Dariusz Koscielnik, Marek Miskowicz
I2C hardware master serial interface for asynchronous ADCs. ISSE (2015)
Dominik Rzepka, Dariusz Koscielnik, Marek Miskowicz
Recovery of varying-bandwidth signal for level-crossing sampling. ETFA (2014)
Dariusz Koscielnik, Marek Miskowicz
Event-driven analog-to-digital converter with conversion-speed-centric architecture and activity-dependent power consumption. ETFA (2013)
Dariusz Koscielnik, Marek Miskowicz, Jakub Szyduczynski
Upper Bounds on Unsuccessful Transmission Rate in Persistent and Non-Persistent CSMA Protocols. ICCCN (2013)
Lukasz Plachno, Marcin Oleksiak, Dariusz Koscielnik, Marek Jableka
I2C interface design for hardware master devices. PDeS (2012)
Dariusz Koscielnik, Marek Miskowicz, Marek Jableka
Natural compression and expansion characteristics of asynchronous Sigma-Delta ADC. ICSPCS (2011)
Dariusz Koscielnik, Marek Miskowicz
Evaluating Maximum Transmission Unreliability in Persistent CSMA Protocol. ICINCO (1) (2010)
Marek Miskowicz, Dariusz Koscielnik
Modeling end-to-end reliability in best-effort networked embedded systems. ETFA (2010)
Dariusz Koscielnik
Simulation Study of the Influence of the Hidden and Exposed Stations for the Efficiency of IEEE 802.15.4 LR-WPAN Networks. Wirel. Sens. Netw. 2 (1) (2010)
Dariusz Koscielnik, Marek Miskowicz
Towards Asynchronous Signal Processing. ICINCO-SPSMC (2009)
Dariusz Koscielnik, Marek Miskowicz
C Interface. ETFA (2009)
Dariusz Koscielnik
The Structure of a Control Network Integrated with the S-bus of an ISDN Network. ICN (2007)
Dariusz Koscielnik, Marek Miskowicz
Designing Time-to-Digital Converter for Asynchronous ADCs. DDECS (2007)
Dariusz Koscielnik
Analysis of IEEE 802.11E Standard in Terms of Real Time Application Requirements. ICWMC (2006)