Chethan Rao

Publication Activity (10 Years)

Years Active: 2009-2014
Publications (10 Years): 0

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Publications

Socrates D. Vamvakos, Charles Boecker, Eric Groen, Alvin Wang, Shaishav Desai, Scott Irwin, Vithal Rao, Aldo Bottelli, Jawji Chen, Xiaole Chen, Prashant Choudhary, Kuo-Chiang Hsieh, Paul Jennings, Haidang Lin, Dan Pechiu, Chethan Rao, Jason Yeung
A 8.125-15.625 Gb/s SerDes using a sub-sampling ring-oscillator phase-locked loop. CICC (2014)
Socrates D. Vamvakos, Claude R. Gauthier, Chethan Rao, Karthisha Ramoshan Canagasaby, Prashant Choudhary, Sanjay Dabral, Shaishav Desai, Mahmudul Hassan, Kuo-Chiang Hsieh, Bendik Kleveland, Gurupada Mandal, Richard Rouse, Ritesh Saraf, Alvin Wang, Jason Yeung, Khaldoon Abugharbieh, Ying Cao
A 2.488-11.2 Gb/s multi-protocol SerDes in 40nm low-leakage CMOS for FPGA applications. MWSCAS (2012)
Socrates D. Vamvakos, Bendik Kleveland, Dipak K. Sikdar, B. K. Ahuja, Haidang Lin, Jayaprakash Balachandran, Wignes Balakrishnan, Aldo Bottelli, Jawji Chen, Xiaole Chen, Jae Choi, Jeong Choi, Rajesh Chopra, Sanjay Dabral, Kalyan Dasari, Ronald B. David, Shaishav Desai, Claude R. Gauthier, Mahmudul Hassan, Kuo-Chiang Hsieh, Ramosan Canagasaby, Jeff Kumala, E. P. Kwon, Ben Lee, Ming Liu, Gurupada Mandal, Sundari Mitra, Byeong Cheol Na, Siddharth Panwar, Jay Patel, Chethan Rao, Vithal Rao, Richard Rouse, Ritesh Saraf, Subramanian Seshadri, Jae-K. Sim, Clement Szeto, Alvin Wang, Jason Yeung
A 576 Mb DRAM with 16-channel 10.3125Gbps serial I/O and 14.5 ns latency. ESSCIRC (2012)
Chethan Rao, Alvin Wang, Shaishav Desai
A 0.46ps RJrms 5GHz wideband LC PLL for multi-protocol 10Gb/s SerDes. CICC (2009)