Cédric Bourrasset

Publication Activity (10 Years)

Years Active: 2013-2018
Publications (10 Years): 12

Top Venues

ICDSC

CoRR

J. Real Time Image Process.

IEEE Signal Process. Lett.

Blaise Pascal University, Clermont-Ferrand, France (PHD)

Education History

Blaise Pascal University, Clermont-Ferrand, France

PHD

Publications

Luca Maggiani, Cédric Bourrasset, Jean-Charles Quinton, François Berry, Jocelyn Sérot
Bio-inspired heterogeneous architecture for real-time pedestrian detection applications. J. Real Time Image Process. 14 (3) (2018)
Cédric Bourrasset, France Boillod-Cerneux, Ludovic Sauge, Myrtille Deldossi, Francois Wellenreiter, Rajesh Bordawekar, Susan Malaika, Jean-Armand Broyelle, Marc West, Brian M. Belgodere
Requirements for an Enterprise AI Benchmark. TPCTC (2018)
Kamel Abdelouahab, Cédric Bourrasset, Maxime Pelcat, François Berry, Jean-Charles Quinton, Jocelyn Sérot
A Holistic Approach for Optimizing DSP Block Utilization of a CNN implementation on FPGA. CoRR (2017)
Kamel Abdelouahab, Maxime Pelcat, Jocelyn Sérot, Cédric Bourrasset, François Berry
Tactics to Directly Map CNN Graphs on Embedded FPGAs. IEEE Embed. Syst. Lett. 9 (4) (2017)
Kamel Abdelouahab, Maxime Pelcat, Cédric Bourrasset, François Berry, Jocelyn Sérot
Tactics to Directly Map CNN graphs on Embedded FPGAs. CoRR (2017)
Kamel Abdelouahab, Maxime Pelcat, Jocelyn Sérot, François Berry, Cédric Bourrasset, Jean-Charles Quinton
Hardware Automated Dataflow Deployment of CNNs. CoRR (2017)
Cédric Bourrasset, Luca Maggiani, Jocelyn Sérot, François Berry
Dataflow object detection system for FPGA-based smart camera. IET Circuits Devices Syst. 10 (4) (2016)
Kamel Abdelouahab, Cédric Bourrasset, Maxime Pelcat, François Berry, Jean-Charles Quinton, Jocelyn Sérot
A Holistic Approach for Optimizing DSP Block Utilization of a CNN implementation on FPGA. ICDSC (2016)
Maxime Pelcat, Cédric Bourrasset, Luca Maggiani, François Berry
Design productivity of a high level synthesis compiler versus HDL. SAMOS (2016)
Jocelyn Sérot, François Berry, Cédric Bourrasset
High-level dataflow programming for real-time image processing on smart cameras. J. Real Time Image Process. 12 (4) (2016)
Luca Maggiani, Cédric Bourrasset, François Berry, Jocelyn Sérot, Matteo Petracca, Claudio Salvadori
Parallel image gradient extraction core for FPGA-based smart cameras. ICDSC (2015)
Luca Maggiani, Cédric Bourrasset, Matteo Petracca, François Berry, Paolo Pagano, Claudio Salvadori
HOG-Dot: A Parallel Kernel-Based Gradient Extraction for Embedded Image Processing. IEEE Signal Process. Lett. 22 (11) (2015)
Cédric Bourrasset, Luca Maggiani, Jocelyn Sérot, François Berry, Paolo Pagano
Distributed FPGA-based smart camera architecture for computer vision applications. ICDSC (2013)
Cédric Bourrasset, Luca Maggiani, Jocelyn Sérot, François Berry, Paolo Pagano
DreamCAM: A FPGA-based platform for smart camera networks. ICDSC (2013)
Cédric Bourrasset, Jocelyn Sérot, François Berry
FPGA-based smart camera mote for pervasive wireless network. ICDSC (2013)

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Publication Activity (10 Years)

Top Topics

Top Venues

Cédric Bourrasset