Bernhard Wess

Publication Activity (10 Years)

Years Active: 1994-2006
Publications (10 Years): 0

Publications

Markus Rupp, Bernhard Wess, Shuvra S. Bhattacharyya
Design Methods for DSP Systems. EURASIP J. Adv. Signal Process. 2006 (2006)
Thomas Zeitlhofer, Bernhard Wess
Integrated assignment of registers and functional units for heterogeneous vliw-architectures. SoCC (2005)
Bernhard Wess, Thomas Zeitlhofer
On the Phase Coupling Problem Between Data Memory Layout Generation and Address Pointer Assignment. SCOPES (2004)
Bernhard Wess, Thomas Zeitlhofer
Optimum address pointer assignment for digital signal processors. ICASSP (5) (2004)
Thomas Zeitlhofer, Bernhard Wess
A comparison of graph coloring heuristics for register allocation based on coalescing in interval graphs. ISCAS (4) (2004)
Thomas Zeitlhofer, Bernhard Wess
List-coloring of interval graphs with application to register assignment for heterogeneous register-set architectures. Signal Process. 83 (7) (2003)
Thomas Zeitlhofer, Bernhard Wess
Optimum register assignment for heterogeneous register-set architectures. ISCAS (3) (2003)
Bernhard Wess
Simulated evolutionary code generation for heterogeneous memory-register DSP-architectures. EUSIPCO (2000)
Stefan Fröhlich, Martin Gotschlich, Udo Krebelder, Bernhard Wess
Dynamic trellis diagrams for optimized DSP code generation. ISCAS (3) (1999)
Bernhard Wess
Minimization of Data Address Computation Overhead in DSP Programs. Des. Autom. Embed. Syst. 4 (2-3) (1999)
Thomas Zeitlhofer, Bernhard Wess
Operation scheduling for parallel functional units using genetic algorithms. ICASSP (1999)
Bernhard Wess, Martin Gotschlich
Minimization of data address computation overhead in DSP programs. ICASSP (1998)
Werner Kreuzer, Bernhard Wess
Cooperative register assignment and code compaction for digital signal processors with irregular datapaths. ICASSP (1997)
Bernhard Wess, Martin Gotschlich
Constructing memory layouts for address generation units supporting offset 2 access. ICASSP (1997)
Bernhard Wess
Code generation based on trellis diagrams. Code Generation for Embedded Processors (1994)