Ashay Rane

Publication Activity (10 Years)

Years Active: 2011-2020
Publications (10 Years): 5

Top Topics

Insertions And Deletions

Efficient Execution

Top Venues

USENIX Security Symposium

ACM Trans. Parallel Comput.

Publications

Dennis Abts, Jonathan Ross, Jonathan Sparling, Mark Wong-VanHaren, Max Baker, Tom Hawkins, Andrew Bell, John Thompson, Temesghen Kahsai, Garrin Kimmell, Jennifer Hwang, Rebekah Leslie-Hurd, Michael Bye, E. R. Creswick, Matthew Boyd, Mahitha Venigalla, Evan Laforge, Jon Purdy, Purushotham Kamath, Dinesh Maheshwari, Michael Beidler, Geert Rosseel, Omar Ahmad, Gleb Gagarin, Richard Czekalski, Ashay Rane, Sahil Parmar, Jeff Werner, Jim Sproch, Adrian Macias, Brian Kurtz
Think Fast: A Tensor Streaming Processor (TSP) for Accelerating Deep Learning Workloads. ISCA (2020)
Lucian Mogosanu, Ashay Rane, Nathan Dautenhahn
MicroStache: A Lightweight Execution Context for In-Process Safe Region Isolation. RAID (2018)
Barry Bond, Chris Hawblitzel, Manos Kapritsos, K. Rustan M. Leino, Jacob R. Lorch, Bryan Parno, Ashay Rane, Srinath T. V. Setty, Laure Thompson
Vale: Verifying High-Performance Cryptographic Assembly Code. USENIX Security Symposium (2017)
Karthikeyan Bhargavan, Barry Bond, Antoine Delignat-Lavaud, Cédric Fournet, Chris Hawblitzel, Catalin Hritcu, Samin Ishtiaq, Markulf Kohlweiss, Rustan Leino, Jay R. Lorch, Kenji Maillard, Jianyang Pan, Bryan Parno, Jonathan Protzenko, Tahina Ramananandro, Ashay Rane, Aseem Rastogi, Nikhil Swamy, Laure Thompson, Peng Wang, Santiago Zanella Béguelin, Jean Karim Zinzindohoue
Everest: Towards a Verified, Drop-in Replacement of HTTPS. SNAPL (2017)
Ashay Rane, Calvin Lin, Mohit Tiwari
Secure, Precise, and Fast Floating-Point Operations on x86 Processors. USENIX Security Symposium (2016)
Ashay Rane, Calvin Lin, Mohit Tiwari
Raccoon: Closing Digital Side-Channels through Obfuscated Execution. USENIX Security Symposium (2015)
Ashay Rane, Rakesh Krishnaiyer, Chris J. Newburn, James C. Browne, Leonardo Fialho, Zakhar Matveev
Unification of Static and Dynamic Analyses to Enable Vectorization. LCPC (2014)
Ashay Rane, James C. Browne
Enhancing Performance Optimization of Multicore/Multichip Nodes with Data Structure Metrics. ACM Trans. Parallel Comput. 1 (1) (2014)
Ashay Rane, James C. Browne
Enhancing performance optimization of multicore chips and multichip nodes with data structure metrics. PACT (2012)
Ashay Rane, James C. Browne, Lars Koesterke
A systematic process for efficient execution on Intel's heterogeneous computation nodes. XSEDE (2012)
Ashay Rane, James C. Browne
Performance Optimization of Data Structures Using Memory Access Characterization. CLUSTER (2011)
Ashay Rane, Saurabh Sardeshpande, James C. Browne
Poster: determining code segments that can benefit from execution on GPUs. SC Companion (2011)