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Ariel L. Pola
Publication Activity (10 Years)
Years Active: 2011-2017
Publications (10 Years): 3
Top Topics
Blind Equalization
Communication Systems
Neural Architecture
High Speed
Top Venues
LATINCOM
IEEE Trans. Circuits Syst. I Regul. Pap.
J. Electr. Comput. Eng.
ISCAS
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Publications
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Benjamin T. Reyes
,
Raul M. Sanchez
,
Ariel L. Pola
,
Mario R. Hueda
Design and Experimental Evaluation of a Time-Interleaved ADC Calibration Algorithm for Application in High-Speed Communication Systems.
IEEE Trans. Circuits Syst. I Regul. Pap.
(5) (2017)
Genaro Bergero
,
Damian A. Morero
,
Ariel L. Pola
,
Mario A. Castrillon
,
Mario R. Hueda
Design and FPGA verification of a quasi-cyclic LDPC code for optical communication systems.
LATINCOM
(2016)
Raul M. Sanchez
,
Benjamin T. Reyes
,
Ariel L. Pola
,
Mario Rafael Hueda
An FPGA-based emulation platform for evaluation of time-interleaved ADC calibration systems.
LASCAS
(2016)
Ariel L. Pola
,
Juan E. Cousseau
,
Oscar E. Agazzi
,
Mario Rafael Hueda
Efficient decision feedforward equalizer with parallelizable architecture.
ISCAS
(2013)
Ariel L. Pola
,
Juan E. Cousseau
,
Oscar E. Agazzi
,
Mario Rafael Hueda
A Low-Complexity Decision Feedforward Equalizer Architecture for High-Speed Receivers on Highly Dispersive Channels.
J. Electr. Comput. Eng.
2013 (2013)
Ariel L. Pola
,
Diego E. Crivelli
,
Juan E. Cousseau
,
Oscar E. Agazzi
,
Mario Rafael Hueda
A new low complexity iterative equalization architecture for high-speed receivers on highly dispersive channels: Decision feedforward equalizer (DFFE).
ISCAS
(2011)