Andrew J. Bennett

Publication Activity (10 Years)

Years Active: 1993-2008
Publications (10 Years): 0

Publications

Andrew J. Bennett, Roy L. Johnston, Eleanor Turpin, Jun Q. He
Analysis of an Immune Algorithm for Protein Structure Prediction. Informatica (Slovenia) 32 (3) (2008)
Andrew J. Bennett, A. J. Field
Performance Engineering with the UML Profile for Schedulability, Performance and Time: A Case Study. MASCOTS (2004)
Andrew J. Bennett, A. J. Field, C. Murray Woodside
Experimental Evaluation of the UML Profile for Schedulability, Performance, and Time. UML (2004)
Andrew J. Bennett, Michel L. F. Grech, Musa R. Unmehopa, Kumar V. Vemuri
Service mediation standards. Bell Labs Tech. J. 7 (3) (2003)
Andrew J. Bennett, Musa R. Unmehopa, Kumar V. Vemuri
The Parlay proxy manager - Architecture considerations. Bell Labs Tech. J. 7 (3) (2003)
Andrew J. Bennett, Paul H. J. Kelly, Ross A. Paterson
Pipelined functional tree accesses and updates: scheduling, synchronization, caching and coherence. J. Funct. Program. 11 (4) (2001)
Andrew J. Bennett, Paul H. J. Kelly
Efficient shared-memory support for parallel graph reduction. Future Gener. Comput. Syst. 12 (6) (1997)
Andrew J. Bennett, Paul H. J. Kelly, Jacob G. Refstrup, Sarah A. M. Talbot
Using Proxies to Reduce Controller Contention in Large Shared-Memory Multiprocessors. Euro-Par, Vol. II (1996)
Sarah A. M. Talbot, Andrew J. Bennett, Paul H. J. Kelly
Cautions, Machine-Independent Performance Tuning for Shared-Memory Multiprocessors. Euro-Par, Vol. I (1996)
Andrew J. Bennett, A. J. Field, Peter G. Harrison
Modelling and Validation of Shared Memory Coherency Protocols. Perform. Evaluation (4) (1996)
Andrew J. Bennett, Paul H. J. Kelly
Eliminating Invalidation in Coherent-Cache Parallel Graph Reduction. PARLE (1994)
Andrew J. Bennett, Paul H. J. Kelly, Ross A. Paterson
Derivation and performance of a pipelined transaction processor. SPDP (1994)
Andrew J. Bennett, Paul H. J. Kelly
Localtiy and False Sharing in Coherent-Cache Parallel Graph Reduction. PARLE (1993)