Andreas Lööw

Publication Activity (10 Years)

Years Active: 2019-2024
Publications (10 Years): 9

Top Topics

Formal Verification

Information Flows

Development Environment

Top Venues

Publications

Andreas Lööw, Daniele Nantes-Sobrinho, Sacha-Élie Ayoun, Caroline Cronjäger, Petar Maksimovic, Philippa Gardner
Compositional Symbolic Execution for Correctness and Incorrectness Reasoning (Extended Version). CoRR (2024)
Ning Dong, Roberto Guanciale, Mads Dam, Andreas Lööw
Formal Verification of Correctness and Information Flow Security for an In-Order Pipelined Processor. FMCAD (2023)
Petar Maksimovic, Caroline Cronjäger, Andreas Lööw, Julian Sutherland, Philippa Gardner
Exact Separation Logic: Towards Bridging the Gap Between Verification and Bug-Finding. ECOOP (2023)
Andreas Lööw
Reconciling Verified-Circuit Development and Verilog Development. FMCAD (2022)
Petar Maksimovic, Caroline Cronjäger, Julian Sutherland, Andreas Lööw, Sacha-Élie Ayoun, Philippa Gardner
Exact Separation Logic. CoRR (2022)
Andreas Lööw
A small, but important, concurrency problem in Verilog's semantics? (Work in progress). MEMOCODE (2022)
Andreas Lööw
Lutsig: a verified Verilog compiler for verified circuit development. CPP (2021)
Andreas Lööw, Magnus O. Myreen
A proof-producing translator for verilog development in HOL. FormaliSE@ICSE (2019)
Andreas Lööw, Ramana Kumar, Yong Kiam Tan, Magnus O. Myreen, Michael Norrish, Oskar Abrahamsson, Anthony C. J. Fox
Verified compilation on a verified processor. PLDI (2019)