André Seffrin

Publication Activity (10 Years)

Years Active: 2009-2012
Publications (10 Years): 0

Top Venues

FPL

FPGA

Darmstadt University of Technology (PHD)

Education History

Darmstadt University of Technology

PHD

Publications

André Seffrin, Sorin A. Huss
Constraint-driven automatic generation of interconnect for partially reconfigurable architectures (abstract only). FPGA (2012)
Florian Benz, André Seffrin, Sorin A. Huss
Bil: A tool-chain for bitstream reverse-engineering. FPL (2012)
H. Gregor Molter, André Seffrin, Sorin A. Huss
State space optimization within the DEVS model of computation for timing efficiency. VLSI-SoC (2011)
André Seffrin, Sorin A. Huss
Determining Minimum Interconnect for Reconfigurable Hardware by Analysis and Verification of Pi-Calculus Design Specifications. MBMV (2011)
André Seffrin, Sorin A. Huss
Hardware-accelerated execution of Pi-calculus reconfiguration schedules. FPT (2011)
André Seffrin, Sorin A. Huss
Ensuring Secure Information Flow in Partially Reconfigurable Architectures by Means of Process Algebra Analysis. TrustCom (2011)
André Seffrin, Sorin A. Huss
Minimal physical resource allocation of pi-calculus schedules to dynamically reconfigurable platforms. DDECS (2011)
André Seffrin, Alexander Biedermann, Sorin A. Huss
Tiny-Pi: A Novel Formal Method for Specification, Analysis and Verification of Dynamic Partial Reconfiguration Processes. FDL (2010)
André Seffrin, Sunil Malipatlolla, Sorin A. Huss
A novel design flow for tamper-resistant self-healing properties of FPGA devices without configuration readback capability. FPT (2010)
H. Gregor Molter, André Seffrin, Sorin Alexander Huss
DEVS2VHDL: Automatic transformation of XML-specified DEVS Model of Computation into synthesizable VHDL code. FDL (2009)

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Publication Activity (10 Years)

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André Seffrin