Abhaya Asthana

Publication Activity (10 Years)

Years Active: 1978-2023
Publications (10 Years): 6

Top Topics

Root Mean Square Error

Software Reliability

Anomaly Detection

Learning Algorithm

Top Venues

ISSRE Workshops

Int. J. Netw. Manag.

Publications

Prachi Chitnis, Abhaya Asthana
Finding Needle in a Haystack: An Algorithm for Real-Time Log Anomaly Detection with Real-Time Learning. ISSREW (2023)
Rashid Mijumbi, Abhaya Asthana, Markku Koivunen, Fu Haiyong, Qinjun Zhu
Design, implementation, and evaluation of learning algorithms for dynamic real-time network monitoring. Int. J. Netw. Manag. 31 (4) (2021)
Rashid Mijumbi, Abhaya Asthana, Carlos Bernal, Manuel Castejón
MAYOR: Machine Learning and Analytics for Automated Operations and Recovery. ICCCN (2019)
Rashid Mijumbi, Kazuhira Okumoto, Abhaya Asthana, Jacques Meekel
Recent Advances in Software Reliability Assurance. ISSRE Workshops (2018)
Rashid Mijumbi, Abhaya Asthana, Markku Koivunen, Fu Haiyong, Zhu Norman
DARN: Dynamic Baselines for Real-time Network Monitoring. NetSoft (2018)
Kazuhira Okumoto, Abhaya Asthana, Rashid Mijumbi
BRACE: Cloud-Based Software Reliability Assurance. ISSRE Workshops (2017)
Abhaya Asthana, Kazu Okumoto
Integrative Software Design for Reliability: Beyond Models and Defect Prediction. Bell Labs Tech. J. 17 (3) (2012)
Abhaya Asthana, Robert S. Blake, Richard D. Jordan, Reza Shafie-Khorasani, Daryl J. Steen
End-to-end service availability support: Theory and application. Bell Labs Tech. J. 15 (1) (2010)
Abhaya Asthana, Eric J. Bauer, Meenakshi Sharma, Xuemei Zhang
End-to-end availability considerations for services over IMS. Bell Labs Tech. J. 11 (3) (2006)
Bernard L. Malone III, Abhaya Asthana
Analyzing network availability of a mobile data network: A case study. Bell Labs Tech. J. 11 (3) (2006)
Harvey I. Epstein, Abhaya Asthana, Stephen A. Corum, Leen Mak
Hybrid network management. Bell Labs Tech. J. 5 (4) (2000)
Abhaya Asthana, Paul Krzyzanowski
A Parallel Architecture for Network Control and Mobility Tracking in Wireless Systems. Wirel. Pers. Commun. 4 (2) (1997)
Abhaya Asthana, Nandit Soparkar, H. V. Jagadish, Paul Krzyzanowski
Logic-enhanced memory for high performance databases. KES (2) (1997)
Abhaya Asthana, James Sienicki, Mani B. Srivastava
Kaleido: An Environment for Composing Networked Multimedia Applications. HPDC (1997)
Nandit Soparkar, Paul Krzyzanowski, H. V. Jagadish, Abhaya Asthana
Run-Time Parallelization of Sequential Database Programs. CIKM (1995)
Abhaya Asthana, Mark Cravatts, Paul Krzyzanowski
An Experimental Active-Memory-Based Network Environment. HPDC (1994)
Abhaya Asthana, Mark Cravatts, Paul Krzyzanowski
An Indoor Wireless System for Personalized Shopping Assistance. WMCSA (1994)
Abhaya Asthana, Paul Krzyzanowski
A Memory Participative Architecture for High Performance Communication Systems. INFOCOM (1994)
Abhaya Asthana, Mark Cravatts, Paul Krzyzanowski
SWIM Active Memory: Architecture and Applications. IFIP Congress (1) (1994)
Abhaya Asthana, Mike Laznovsky, Boyd Mathews
SEMU: A Parallel Processing System for Timing Simulation of Digital CMOS VLSI Circuits. VLSI Design (1994)
Abhaya Asthana, Mark Cravatts, Paul Krzyzanowski
Towards a Programming Environment for a Computer with Intelligent Memory. IFIP PACT (1994)
Abhaya Asthana, Mark Cravatts, Paul Krzyzanowski
An experimental active memory based I/O subsystem. SIGARCH Comput. Archit. News 22 (4) (1994)
Abhaya Asthana, Catherine Delph, H. V. Jagadish, Paul Krzyzanowski
Towards a Gigabit IP Router. J. High Speed Networks 1 (4) (1992)
Abhaya Asthana, H. V. Jagadish, Paul Krzyzanowski
The Design of a Back-end Object Management System. Code Generation (1991)
Abhaya Asthana, H. V. Jagadish, Scott C. Knauer
An Intelligent Memory Transaction Engine. IWDM (1989)
Abhaya Asthana, Cheryl J. Briggs, Mark R. Cravats, Boyd Mathews
The Architecture of Massively Parallel Numeric Processor. IFIP Congress (1989)
Abhaya Asthana, H. V. Jagadish, Boyd Mathews
Impact of Advanced VLSI Packaging on the Design of a Large Parallel Computer. ICPP (1) (1989)
Abhaya Asthana, Boyd Mathews, Cheryl J. Briggs, Mark R. Cravats
A VLSI Building Block for Massively Parallel Computation. FGCS (1988)
J. A. Chandross, H. V. Jagadish, Abhaya Asthana
The trap as a control flow mechanism. MICRO (1988)
Abhaya Asthana, H. V. Jagadish, J. A. Chandross, D. Lin, Scott C. Knauer
An intelligent memory system. SIGARCH Comput. Archit. News 16 (4) (1988)
Sudhir Ahuja, Abhaya Asthana
A Multi-Microprocessor Architecture with Hardware Support for Communication and Scheduling. ASPLOS (1982)
Abhaya Asthana
Design and Control of a Three-Stage Switch Matrix in the Presence of Fan-Out. IEEE Trans. Computers 27 (10) (1978)